1. Field of the Invention
The present invention relates to an integrated circuit MOS-type semiconductor device. More particularly, the present invention relates to a memory cell array of a MOS-type memory device.
2. Description of the Related Art
In a general integrated circuit MOS-type semiconductor device, elements are separated from each other by a field oxide film. A source region and a drain region are formed by masking a gate electrode and implanting an impurity into a substrate by a self-aligning method. It is necessary to dispose one or two contact portions between the source and drain regions with respect to one transistor so that high integration is prevented by a contact margin and a wiring pitch.
To solve this problem, a semiconductor integrated circuit device having a so-called planar cell structure is proposed in Laid-Open Japanese Patent applications (KOKAI) Nos. 61-288464, 63-96953, etc.
High density and high integration are desirable for semiconductor memory devices as well as other integrated circuit devices. To provide a fine structure for a memory cell array having the planar cell structure, it is necessary to reduce the pitch of diffusion regions and word lines. However, one limitation is the performance of an apparatus for manufacturing the memory cell array, which tends to limit pitch to 2 .mu.m in the present manufacturing apparatus for mass production.